3rd Workshop on
High-performance and Real-time Embedded Systems
(HiRES 2015)

January 21, 2015, Amsterdam, the Netherlands

To be held in conjunction with the
10th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC 2015)


News: Presentations are available


Goal of the Workshop

Increasingly, time is a relevant concern which impacts in all application areas and challenges ahead. Real-time requirements can be found in applications ranging from large-scale data processing systems to deeply embedded devices. Examples include safety-critical systems with high-performance requirements, such as collision avoidance and autonomous driving in avionics and automotive respectively, in which the correct timing behaviour is of paramount importance; consumer systems, such as video processing in TV sets and games; or real-time complex event processing applications, such as online trading or real-time traffic management.

In all these applications, systems are expected to cope with an increasing demand of functional and non-functional requirements, with the corresponding increase in processing capabilities, paving the way for high-performance architectures, of which multi-core and many-core systems are becoming pervasive. The capabilities and challenges of parallelization as a means to provide higher performance is a cross-cutting concern.

This workshop intends to bring together researchers and engineers in the confluence of high-performance, embedded systems and real-time systems. The goal is to allow for fruitful discussions on the challenges and research directions that should be tackled by the community. Papers and presentations illustrate current and future work in the theory and practice of the design and engineering of high-performance real-time embedded systems for a variety of application domains.

This is the 3rd workshop in the series. Information on previous workshop can be found at HiRES 2013 and HiRES 2014.



Workshop Program (Preliminary)

Room: G107

10:00-11:00 Welcome & Keynote

Session Chair: Luis Miguel Pinho

In the opening talk of the workshop, Eric Debes, responsible for computing R&T strategy for Thales, will present a perspective on the challenges of high-performance and real-time embedded systems.

11:00-11:30 Coffee Break

11:30-13:00 Paper Session #1
Session Chair: Eduardo Quiñones

Experiences and Results of Parallelisation of Industrial Hard Real-time Applications for the parMERASA Multi-core (

Theo Ungerer, Christian Bradatsch, Martin Frieb, Florian Kluge, Jörg Mische, Alexander Stegmeier, Ralf Jahr, Mike Gerdes, Pavel Zaykov, Lucie Matusova, Zai Jian Jia Li, Zlatko Petrov, Bert Böddeker, Sebastian Kehr, Hans Regler, Andreas Hugl, Christine Rochange, Haluk Ozaktas, Hugues Cassé, Armelle Bonenfant, Pascal Sainrat, Nick Lay, David George, Ian Broster, Eduardo Quiñones, Milos Panic, Jaume Abella, Carles Hernandez, Francisco Cazorla, Sacha Uhrig, Mathias Rohde and Arthur Pyka

WCET Analysis of Parallel Benchmarks using On-Demand Coherent Cache (Presentation)

Arthur Pyka, Lillian Tadros, Sascha Uhrig, Hugues Cassé, Haluk Ozaktas and Christine Rochange

Partitioning Algorithm for Mixed Criticality Systems (Presentation)

Emilio Salazar and Alejandro Alonso

13:00-14:00 Lunch Break

14:15-15:15 Paper Session #2
Session Chair: Sascha Uhrig

Algorithmic Skeletons for Parallelization of Embedded Real-time Systems (

Alexander Stegmeier, Martin Frieb, Ralf Jahr and Theo Ungerer

A system model and stack for the parallelization of time-critical applications on many-core architectures (Presentation)

Vincent Nelis, Patrick Meumeu Yomsi, Luis Miguel Pinho, Eduardo Quiñones, Marko Bertogna, Andrea Marongiu, Paolo Gai and Claudio Scordino

15:15-16:00 Break

16:00-17:30 Panel: Challenges of Timing Analysis of Many-Core Platforms
Moderator: Luis Miguel Pinho

With the increasing interest on many-core platforms for high-performance real-time systems, it is more and more challenging how to derive safe and accurate worst-case execution times.


The panel will include the perspective on the topic of prominent experts in the area:

-       Christian Ferdinand, AbsInt

-       Francisco Cazorla, BSC

-       Luca Fossati, ESA

-       Sebastian Altmeyer, UvA


The panel is in conjunction with the TACLe Workshop.


17:30 (Closing)



Topics of interest

Topics of interest to this edition of the workshop include but are not limited to:

-              Runtimes and operating systems combining high-performance and predictability requirements;

-              Programming models and compiler support for providing real-time capabilities to multi- and many-core architectures;

-              Models and tools for code generation, system verification and validation;

-              Worst-case execution time analysis, parallel/dag-based task models, schedulability analysis of multi- and many-core systems; 

-              Heterogeneous multi-core embedded real-time architectures, many-core accelerators;

-              Time-predictable multi- and many-core processor architectures;

-              Time-aware energy-efficiency.


Paper submission

Submitted papers should use the LNCS format and should be 12 pages maximum. Submissions are handled through easychair at https://www.easychair.org/conferences/?conf=hires2015.

HiRES goals are to allow for interaction and discussion on early results. Informal proceedings will be provided to the participants and online on the workshop website, but no formal publication will be provided.


Important dates

Submission deadline: Abstract registration - October 20, 2014
                                      Paper submission    - October 27, 2014

Notification to authors: November 23, 2014

Final version of accepted papers: December 9, 2014

Workshop: January 21, 2015



Luís Miguel Pinho, CISTER, Portugal

Eduardo Quiñones, BSC, Spain

Sascha Uhrig, TU Dortmund, Germany


Program committee

Albert Cohen, INRIA, France

Alejandro Alonso, Universidad Politécnica de Madrid, Spain

Andrea Marongiu, ETHZ, Switzerland

Eduardo Quiñones, BSC, Spain

Johan Eker, Ericsson, Sweden

Luís Miguel Pinho, CISTER, Portugal

Marko Bertogna, University of Modena, Italy

Martin Schoeberl, DTU, Denmark

Mats Brorsson, KTH, Sweden

Neil Audsley, University of York, UK

Philippe Bonnot, Thales, France

Sascha Uhrig, TU Dortmund, Germany

Theo Ungerer, University of Augsburg, Germany

Zlatko Petrov, Honeywell, Czech Republic