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Conference or Workshop Papers
Multicore in Real-Time Systems – Temporal Isolation Challenges due to Shared Resources CISTER-TR-140302 
Ondrej Kotaba, Jan Nowotsch, Michael Paulitsch, Stefan M. Petters, Henrik TheilingWorkshop on Industry-Driven Approaches for Cost-effective Certification of Safety-Critical, Mixed-Criticality Systems (WICERT 2013). 22, Mar, 2013. Grenoble, France.
Conservative Open-page Policy for Mixed Time-Criticality Memory Controllers CISTER-TR-130104 
Sven Goossens, Benny Åkesson, Kees GoossensDesign, Automation & Test in Europe Conference & Exhibition (DATE 2013), IEEE. 18 to 22, Mar, 2013, pp 525-530. Grenoble, France.
Bounding SDRAM Interference: Detailed Analysis vs. Latency-Rate Analysis CISTER-TR-130105 
Hardik Shah, Alois Knoll, Benny ÅkessonDesign, Automation & Test in Europe Conference & Exhibition (DATE 2013), IEEE. 18 to 22, Mar, 2013, pp 308-313. Grenoble, France.
System and Circuit Level Power Modeling of Energy-Efficient 3D-Stacked Wide I/O DRAMs CISTER-TR-130106 
Karthik Chandrasekar, Christian Weis, Benny Åkesson, Norbert Wehn, Kees GoossensDesign, Automation & Test in Europe Conference & Exhibition (DATE 2013), IEEE. 18 to 22, Mar, 2013, pp 236-241. Grenoble, France.
Architecture and Optimal Configuration of a Real-Time Multi-Channel Memory Controller CISTER-TR-130107 
Manil Dev Gomony, Benny Åkesson, Kees GoossensDesign, Automation & Test in Europe Conference & Exhibition (DATE 2013), EDA Consortium San Jose. 18 to 22, Mar, 2013, pp 1307-1312. Grenoble, France.
A Declarative Compositional Timing Analysis for Multicores Using the Latency-Rate Abstraction CISTER-TR-130108 
Vitor Rodrigues, Benny Åkesson, Simão Patrício Melo de Sousa, Mário Florido15th International Symposium on Practical Aspects of Declarative Languages (PADL '13), Springer Berlin Heidelberg. 21 to 22, Jan, 2013, 7752, pp 43-59. Rome, Italy.
Technical Reports
Energy and Pre-emption Savings through Real-Time Race-To-Halt Algorithms CISTER-TR-130507 
Muhammad Ali Awan, Stefan M. Petters30, May, 2013.Technical report


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