PReFECT
Predictable Multiprocessor Platforms for Embedded Safety Critical Systems
| POCI-01-0145-FEDER-029119 PTDC/CCI-COM/29119/2017 42 months (Jul 2018 to Jan 2022) | |
| Summary: | The PReFECT project will address the following challenges with respect to the introduction of multicore processors in safety-critical systems: - model and analyze the timing interference generated by the hardware resources shared between cores (e.g., caches, interconnect and I/O devices); - propose runtime mechanisms and scheduling solutions to mitigate the unpredictability of COTS multicore processors by controlling the interference between cores; - develop tools for the automatic system configuration before its deployment. The goal of this task is to optimize the usage of the platform while guaranteeing that all the timing requirements of the applications are respected. To attain these objectives we will build upon the large body of results already published by the research team on modelling and timing analysis of multicore processors, and on the expertise of the industrial partners (GMV and Critical Software) in the safety critical system development. The project results will be demonstrated in two industrial use-cases related to the avionics and automotive domains. |
| Funding: | Global: 237KEUR, CISTER: 237KEUR |
| Sponsors: |     |
| Partners: | |
| Contact Person at CISTER: | Eduardo Tovar |
14, Dec, 2021
Best Paper Award at ICESS 2021
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Conference or Workshop Papers/Talks
Work-In-Progress: WCRT Analysis for the 3-Phase Task Model in Partitioned Scheduling CISTER-TR-201005
Jatin Arora, Cláudio Maia, Syed Aftab Rashid, Geoffrey Nelissen, Eduardo TovarWork in Progress Session, 41st IEEE Real-Time Systems Symposium (RTSS 2020). 1 to 4, Dec, 2020, pp 407-410. Online.
Jatin Arora, Cláudio Maia, Syed Aftab Rashid, Geoffrey Nelissen, Eduardo TovarWork in Progress Session, 41st IEEE Real-Time Systems Symposium (RTSS 2020). 1 to 4, Dec, 2020, pp 407-410. Online.
PDFImplementing Hybrid Semantics: From Functional to Imperative CISTER-TR-201008
Sergey Goncharov, Renato Neves, José Proença17th International Colloquium on Theoretical Aspects of Computing (ICTAC 2020). 30, Nov to 4, Dec, 2020, pp 262-282. Online.Lecture Notes in Computer Science, vol 12545.
Sergey Goncharov, Renato Neves, José Proença17th International Colloquium on Theoretical Aspects of Computing (ICTAC 2020). 30, Nov to 4, Dec, 2020, pp 262-282. Online.Lecture Notes in Computer Science, vol 12545.
ARx: Reactive Programming for Synchronous Connectors CISTER-TR-200701
José Proença, Guillermina CledouInternational Conference on Coordination Languages and Models (COORDINATION 2020). 15 to 19, Jun, 2020, Coordination Languages, pp 39-56. Online.Held as part of the 15th International Federated Conference on Distributed Computing Techniques (DisCoTec 2020). Part of the Lecture Notes in Computer Science book series (LNCS, volume 12134).
José Proença, Guillermina CledouInternational Conference on Coordination Languages and Models (COORDINATION 2020). 15 to 19, Jun, 2020, Coordination Languages, pp 39-56. Online.Held as part of the 15th International Federated Conference on Distributed Computing Techniques (DisCoTec 2020). Part of the Lecture Notes in Computer Science book series (LNCS, volume 12134).
A Holistic Memory Contention Analysis for Parallel Real-Time Tasks under Partitioned Scheduling CISTER-TR-200801
Daniel Casini, Alessandro Biondi, Geoffrey Nelissen, Giorgio Buttazzo26th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2020). 21 to 24, Apr, 2020, pp 239-252. Online.
Daniel Casini, Alessandro Biondi, Geoffrey Nelissen, Giorgio Buttazzo26th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2020). 21 to 24, Apr, 2020, pp 239-252. Online.
Cache Persistence-Aware Memory Bus Contention Analysis for Multicore Systems CISTER-TR-191102
Syed Aftab Rashid, Geoffrey Nelissen, Eduardo TovarDesign, Automation and Test in Europe Conference (DATE 2020). 9 to 13, Mar, 2020, pp 442-447. Online.
Syed Aftab Rashid, Geoffrey Nelissen, Eduardo TovarDesign, Automation and Test in Europe Conference (DATE 2020). 9 to 13, Mar, 2020, pp 442-447. Online.
From Code to Weakly Hard Constraints: A Pragmatic End-to-End Toolchain for Timed C CISTER-TR-190905
Saranya Natarajan, Mitra Nasri, David Broman, Björn B. Brandenburg, Geoffrey Nelissen40th IEEE Real-Time Systems Symposium (RTSS 2019). 18 to 21, Feb, 2020, pp 167-180. York, United Kingdom.RTSS 2019 originally postponed from December 2019 (Hong-Kong) to February 2020 (York, UK) was cancelled.
Saranya Natarajan, Mitra Nasri, David Broman, Björn B. Brandenburg, Geoffrey Nelissen40th IEEE Real-Time Systems Symposium (RTSS 2019). 18 to 21, Feb, 2020, pp 167-180. York, United Kingdom.RTSS 2019 originally postponed from December 2019 (Hong-Kong) to February 2020 (York, UK) was cancelled.
Thermal-Aware Schedulability Analysis for Fixed-Priority Non-Preemptive Real-Time Systems CISTER-TR-190903
Javier Pérez Rodríguez, Patrick Meumeu Yomsi40th IEEE Real-Time Systems Symposium (RTSS 2019). 18 to 21, Feb, 2020, Real-Time System, pp 154-166. York, United Kingdom.RTSS 2019 originally postponed from December 2019 (Hong-Kong) to February 2020 (York, UK) was cancelled.
Javier Pérez Rodríguez, Patrick Meumeu Yomsi40th IEEE Real-Time Systems Symposium (RTSS 2019). 18 to 21, Feb, 2020, Real-Time System, pp 154-166. York, United Kingdom.RTSS 2019 originally postponed from December 2019 (Hong-Kong) to February 2020 (York, UK) was cancelled.
Technical Reports
Verification of Real-Time Coordination in VirtuosoNext (extended version) CISTER-TR-201010
Guillermina Cledou, José Proença, Bernhard H.C. Sputh, Eric Verhulst8, May, 2020.
Guillermina Cledou, José Proença, Bernhard H.C. Sputh, Eric Verhulst8, May, 2020.