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Vincent Nélis (Publications)

Vincent Nélis (Publications)

Vincent Nélis (Publications)

PhD Université Libre de Bruxelles, Belgium
Research Associate

Vincent Nelis received his Ph.D. degree in 2010, at the age of 25, at the Computer Science Department of the Université Libre de Bruxelles, Belgium. Since then, he has graduated 2 Ph.D. students as main supervisor (both received the highest distinction for their thesis) and one Ph.D. student as co-supervisor. He is currently the main supervisor of a third Ph.D. student and co-supervises a second Ph.D. student.

Vincent Nelis has published more than 40 papers with about 50 different co-authors in international journals, conferences, and workshops. He received 7 awards, contributed to 9 R&D projects, led a Work Package in a European FP7 STREP project, chaired 3 international workshops, and he has been member of the program committee of more than 30 international journals, conferences and workshops. Throughout his short career he has given countless presentations and attended numerous meetings, from simple collaborations with academic peers to project meetings, technical and review meetings.

Currently, his main research interest is in developing methods and tools to derive all sorts of timing estimates for applications running on multicore platforms.

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Conference or Workshop Papers
The P-SOCRATES timing analysis methodology for parallel real-time applications deployed on many-core platforms CISTER-TR-170505 
Vincent Nélis, Patrick Meumeu Yomsi, Luis Miguel Pinho29th Euromicro Conference on Real-Time Systems (ECRTS 2017), Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik. 27 to 30, Jun, 2017, WCET 2017, pp 10:1-10:9. Dubrovnik, Croatia.
Partitioning and Analysis of the Network-on-Chip on a COTS Many-Core Platform CISTER-TR-170302 
Matthias Becker, Borislav Nikolic, Dakshina Dasari, Benny Åkesson, Vincent Nélis, Moris Behnam, Thomas Nolte24th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2017). 18 to 20, Apr, 2017. Pittsburgh, U.S.A..
High-performance parallelisation of real-time applications CISTER-TR-170203 
Luis Miguel Pinho, Vincent Nélis, Eduardo Quinoñes, Paolo Burgio, Andrea Marongiu, Paolo Gai, Juan Sancho
ABSTRACTPDFPDF Additional Files: PDFPresentation
Embedded World Conference 2017. 14 to 16, Mar, 2017, Session 19: HiPEAC – High Performance Embedded Architectures. Nuremberg, Germany.
Technical Reports
Errata: Timing Analysis of Fixed Priority Self-Suspending Sporadic Tasks CISTER-TR-170205 
Geoffrey Nelissen, José Fonseca, Gurulingesh Raravi, Vincent Nélis2017.