REGAIN
Real-time scheduling on general purpose graphics processor units
| FCOMP-01-0124-FEDER-020447 PTDC/EIA-CCO/118080/2010 40 months (Apr 2012 to Jul 2015) | |
| Summary: | Among all processors sold today, 98% are used in embedded computer systems; therefore catering to this segment is of utmost importance. Moreover, there is a persistent trend in computing that techniques originally developed at the high-end (pipelining, cache-memories, instruction-level parallelism) later propagate to embedded computer systems. Graphics processors are the next technology to do this transition. Graphics processors were originally used only for graphics but have evolved significantly during the recent decade as witnessed by the following. First, the performance of graphics processor units has followed the exponential advances in semiconductor density (Moore´s law) whereas the performance of normal processors (CPUs) has not. Second, graphics processor units are increasingly integrated with a normal processor on a single chip for use both in high and low-end computer systems. Intel Sandybridge, AMD Fusion and NVIDIA Tegra 2 exemplify this. Third, today’s graphics processors can multitask and offer fast context switching (25 microseconds) between different applications. Fourth, graphics processors are today able to perform general-purpose computations, using macros in C-programs; this allows normal software developers to use graphics processors for data-parallel programs. Therefore, this type of processor can be viewed as a multicore processor; it has come to be called General Purpose Graphics Processor Unit (GPGPU) or simply GPU (the phenomenon is called GPU computing). Because of its attractive performance, the GPGPU will become the workhorse in virtually all computer systems. Even so, embedded systems pose specific challenges: Embedded computer systems interact with their physical world. For example, a computer which autonomously drives a car (GPUs are intended for this) must not only compute the correct actuation signals (for example steering) but must also do so at the right time in order to drive safely. The real-time systems research community has created a comprehensive toolkit involving (i) algorithms for run-time scheduling of tasks with deadlines and (ii) proof methods (called schedulability tests) for proving before run-time, using a given scheduling algorithm at run-time and given a model of the workload, that all deadlines of tasks are met at run-time. This toolkit (rate-monotonic and earliest-deadline-first scheduling and analysis) is currently well-established for uniprocessors. Scientific work is currently underway for transferring these results to multiprocessors; multicores in particular. Yet, the scientific community in the area of real-time systems offers no scheduling theory for GPGPUs and creating such a theory is non-trivial. Considering the importance of GPGPUs and their expected importance in embedded systems in the future and considering the current lack of scheduling theory for GPGPUs, there is a strong need to create a scheduling theory for GPGPUs. Therefore, this project will create a real-time scheduling theory for GPGPUs. This theory will offer (i) a model suited for describing real-time scheduling on GPGPUs, (ii) algorithms for run-time scheduling of tasks using GPGPUs and (iii) algorithms for proving, before run-time, that tasks using GPGPUs meet their deadlines. This project will also test the theory on commercially available GPGPUs. |
| Funding: | Global: 139KEUR, CISTER: 139KEUR |
| Sponsors: |   |
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| Contact Person at CISTER: | Konstantinos Bletsas |
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Conference or Workshop Papers/Talks
Two Protocols to Reduce the Criticality Level of Multiprocessor Mixed-Criticality Systems CISTER-TR-131004
François Santy, Gurulingesh Raravi, Geoffrey Nelissen, Vincent Nélis, Pratyush Kumar, Joel Goossens, Eduardo Tovar21st International Conference on Real-Time Networks and Systems (RTNS'13), ACM. 16 to 18, Oct, 2013, pp 183-192. Sophia Antipolis, France.
François Santy, Gurulingesh Raravi, Geoffrey Nelissen, Vincent Nélis, Pratyush Kumar, Joel Goossens, Eduardo Tovar21st International Conference on Real-Time Networks and Systems (RTNS'13), ACM. 16 to 18, Oct, 2013, pp 183-192. Sophia Antipolis, France.
PDFFeasibility Intervals for Homogeneous Multicores, Asynchronous Periodic Tasks, and FJP Schedulers CISTER-TR-131005
Vincent Nélis, Patrick Meumeu Yomsi, Joel Goossens21st International Conference on Real-Time Networks and Systems (RTNS 2013), ACM New York. 16 to 18, Oct, 2013, pp 277-286. Sophia Antipolis, France.Best Presentation Award
Vincent Nélis, Patrick Meumeu Yomsi, Joel Goossens21st International Conference on Real-Time Networks and Systems (RTNS 2013), ACM New York. 16 to 18, Oct, 2013, pp 277-286. Sophia Antipolis, France.Best Presentation Award
Faster Makespan Estimation for GPU Threads on a Single Streaming Multiprocessor CISTER-TR-130904
Kostiantyn Berezovskyi, Konstantinos Bletsas, Stefan M. Petters18th IEEE Conference on Emerging Technology and Factory Automation (ETFA 2013), IEEE. 10 to 13, Sep, 2013, pp 1-8. Cagliari, Italy.
Kostiantyn Berezovskyi, Konstantinos Bletsas, Stefan M. Petters18th IEEE Conference on Emerging Technology and Factory Automation (ETFA 2013), IEEE. 10 to 13, Sep, 2013, pp 1-8. Cagliari, Italy.
Response-Time Analysis of Fork/Join Tasks in Multiprocessor Systems CISTER-TR-130701
Cláudio Maia, Luis Miguel Nogueira, Luis Miguel Pinho, Marko BertognaWork in Progress Session, 25th Euromicro Conference on Real-Time Systems (ECRTS 2013). 9 to 12, Jul, 2013. Paris, France.
Cláudio Maia, Luis Miguel Nogueira, Luis Miguel Pinho, Marko BertognaWork in Progress Session, 25th Euromicro Conference on Real-Time Systems (ECRTS 2013). 9 to 12, Jul, 2013. Paris, France.
Scheduling Parallel Real-Time Tasks using a Fixed-Priority Work-Stealing Algorithm on Multiprocessors CISTER-TR-130607
Cláudio Maia, Luis Miguel Nogueira, Luis Miguel Pinho8th IEEE International Symposium on Industrial Embedded Systems (SIES2013). 19 to 21, Jun, 2013. Porto, Portugal.
Cláudio Maia, Luis Miguel Nogueira, Luis Miguel Pinho8th IEEE International Symposium on Industrial Embedded Systems (SIES2013). 19 to 21, Jun, 2013. Porto, Portugal.
Identifying the Sources of Unpredictability in COTS-based Multicore Systems CISTER-TR-130604
Dakshina Dasari, Benny Åkesson, Vincent Nélis, Muhammad Ali Awan, Stefan M. Petters8th IEEE International Symposium on Industrial Embedded Systems (SIES 2013), IEEE. 19 to 21, Jun, 2013, pp 39-48. Porto, Portugal.
Dakshina Dasari, Benny Åkesson, Vincent Nélis, Muhammad Ali Awan, Stefan M. Petters8th IEEE International Symposium on Industrial Embedded Systems (SIES 2013), IEEE. 19 to 21, Jun, 2013, pp 39-48. Porto, Portugal.
On the use of Work-Stealing Strategies in Real-Time Systems CISTER-TR-130110
Luis Miguel Nogueira, Luis Miguel Pinho, José Fonseca, Cláudio MaiaHigh-performance and Real-time Embedded Systems (HiRES 2013). 23, Jan, 2013. Berlin, Germany.In conjunction with the 8th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC 2013)
Luis Miguel Nogueira, Luis Miguel Pinho, José Fonseca, Cláudio MaiaHigh-performance and Real-time Embedded Systems (HiRES 2013). 23, Jan, 2013. Berlin, Germany.In conjunction with the 8th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC 2013)
Technical Reports
Fast Makespan Estimation for GPU Threads on a Single Streaming Multiprocessor CISTER-TR-130406
Kostiantyn Berezovskyi, Konstantinos Bletsas, Stefan M. Petters14, Apr, 2013.
Kostiantyn Berezovskyi, Konstantinos Bletsas, Stefan M. Petters14, Apr, 2013.