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Konstantinos Bletsas (Publications)

Konstantinos Bletsas (Publications)

Konstantinos Bletsas (Publications)

PhD University of York, United Kingdom
Research Associate

Konstantinos Bletsas (born in 1978 in Greece) has a Degree in Electronic and Computer Engineering (2002) from the Technical University of Crete (Chania, Greece) and a PhD in Computer Science (2007) from the University of York (UK). His PhD, supervised by Professor Neil Audsley, was about the response time analysis of hard real-time systems with application-specific co-processors.
He joined the CISTER research unit in 2007, to do research on multiprocessor scheduling algorithms, which has been his main line of work ever since. He has been part of the technical program committees of top-impact conferences in the core real time area, such as ECRTS (2013, 2014, 2015, 2016) , IEEE RTAS (2016) and RTSS (2017) and has supervised one completed PhD.

 

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Conference or Workshop Papers
Mixed-criticality Scheduling with Dynamic Memory Bandwidth Regulation CISTER-TR-180604 
Muhammad Ali Awan, Konstantinos Bletsas, Pedro Souto, Benny Åkesson, Eduardo Tovar24th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2018). 28 to 31, Aug, 2018. Hakodate, Japan.
Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers CISTER-TR-180401 
Muhammad Ali Awan, Pedro F. Souto, Konstantinos Bletsas, Benny Åkesson, Eduardo Tovar30th Euromicro Conference on Real-Time Systems (ECRTS 2018). 3 to 6, Jul, 2018, pp 2:1-2:22. Barcelona, Spain.
Mixed-criticality Scheduling with Memory Bandwidth Regulation CISTER-TR-171201 
Muhammad Ali Awan, Pedro Souto, Konstantinos Bletsas, Benny Åkesson, Eduardo TovarDesign, Automation and Test in Europe 2018 (DATE 2018). 19 to 23, Mar, 2018. Dresden, Germany.
Technical Reports
Mixed-criticality Scheduling with Dynamic Memory Bandwidth Regulation (Long Version) CISTER-TR-180603 
Muhammad Ali Awan, Konstantinos Bletsas, Pedro Souto, Benny Åkesson, Eduardo Tovar28, Aug, 2018.