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Seminar Series 2015 - António Barros

Seminar Series 2015 - António Barros

Real-time scheduling of STM transactions on multi-core platforms
9, Dec, 2015 11:30-12:30 (1 hour)
CISTER, Porto, Portugal

ABSTRACT:
Recent embedded processor architectures containing multiple heterogeneous cores and non-coherent caches renewed attention to the use of Software Trans- actional Memory (STM) as a building block for developing parallel applications. STM promises to ease concurrent and parallel software development, but relies on the possibility of abort conflicting transactions to maintain data consistency, which in turns affects the execution time of tasks carrying transactions. Because of this fact the timing behaviour of the task set may not be predictable, thus it is crucial to limit the execution time overheads resulting from aborts.
In this talk we formalise a FIFO-based algorithm to order the sequence of commits of concurrent transactions. Then, we propose and evaluate two non-preemptive and one SRP-based fully-preemptive scheduling strategies, in order to avoid transaction starvation.

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PDF Presentation (20 MB)



CISTER's main roles:
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António Barros
Speaker

S101 Auditorium/Seminar Room
1st Floor
























































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