Keynote Speakers


Hermann Kopetz, TU Vienna
The Time-Triggered Architecture (TTA)

Abstract: The time-triggered architecture (TTA) provides a computing infrastructure for the design and implementation of dependable distributed embedded systems. A large real-time application is decomposed into nearly autonomous clusters and nodes, and a fault-tolerant global time base of known precision is generated at every node. In the TTA, this global time is used to precisely specify the interfaces among the nodes, to simplify the communication and agreement protocols, to perform prompt error detection, and to guarantee the timeliness of real-time applications. The TTA supports a two-phased design methodology, architecture design, and component design. During the architecture design phase, the interactions among the distributed components and the interfaces of the components are fully specified in the value domain and in the temporal domain. In the succeeding component implementation phase, the components are built, taking these interface specifications as constraints.

This talk presents the architecture model of the TTA, explains the design rationale, discusses the time-triggered communication protocols TTP  and TTEthernet, and illustrates how transparent fault tolerance can be implemented in the TTA.

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Hermann KopetzHermann Kopetz is Professor for Real-Time Systems at the Vienna University of Technology since 1982. He has published a widely used textbook on Real-Time Systems, more than 150 papers and 20 patents on the topic of dependable embedded systems. He is the chief architect of the time-triggered architecture. He is a Life Fellow of the IEEE, a full member of the Austrian Academy of Science, received the IEEE Computer Society 2003 Technical Achievement Award in 2003 and the honorary degree of Dr. honoris causa from the University Paul Sabatier in Toulouse, France in 2007.






David Atienza, EPFL
Thermal-Aware System-Level Design of 2D/3D MPSoC Architectures

Abstract: Multi-Processor Systems-on-Chips (MPSoCs) are penetrating the consumer electronics market as powerful solutions to the growing demand for scalable and high-performance systems, at limited design complexity and power dissipation. Nevertheless, MPSoCs are prone to alarming temperature variations on the die, which seriously decrease their expected reliability and lifetime. Furthermore, technical advances in manufacturing technologies are fueling the trend towards high performance 3D MPSoC designs. However, 3D stacking creates higher power and heat density, leading to further degrading reliability and performance if thermal management is not handled properly. Thus, it is critical to develop dedicated design methodologies that guarantee safe thermal behavior of forthcoming 2D and 3D MPSoCs at low energy and performance cost.

In this talk I will discuss the development of novel system-level design methodologies for 2D and 3D MPSoCs that seamlessly address thermal modeling, analysis and management. First, I will revise thermal modeling mechanisms for 2D MPSoCs based on simulation and emulation frameworks. Second, I will introduce reactive and proactive run-time thermal management methods which prevent hot spots and large thermal gradients in 2D MPSoCs while incurring negligible performance degradation. Finally, I will show how new thermal modeling and active management methods, including liquid cooling, can be modeled and included in this novel design flows for next-generation 3D MPSoC architectures.

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David Atienza

David Atienza is Professor of Electrical Engineering and Director of the Embedded Systems Laboratory (ESL) at EPFL, and Adjunct Professor at the Computer Architecture and Engineering Department of UCM. He received his M.Sc. and Ph.D. degrees in Computer Science and Engineering from UCM, and Inter-University Micro-Electronics Center (IMEC), Belgium, in 2001 and 2005, respectively. His research interests focus on design methodologies for high-performance multi-core embedded systems and low-power Systems-on-Chip (SoC), including new thermal modeling and management techniques for 2D/3D Multi-Processor SoCs, wireless body sensor networks, dynamic memory management and memory hierarchy optimizations, as well as NoC design. In these fields, he is co-author of more than 150 publications in prestigious journals and international conferences. He has received a Best Paper Award at the IEEE/IFIP VLSI-SoC 2009 Conference and two Best Paper Award Nominations at the ICCAD 2006 and DAC 2004 conferences. He is an Associate Editor of IEEE Trans. on CAD, IEEE Letters on Embedded Systems and Elsevier Integration: The VLSI Journal. He is also an elected member of the Executive Committee of the IEEE Council of Electronic Design Automation (CEDA) since 2008 and an elected member of the Board of Governors of the IEEE Circuits and Systems Society (CASS) since 2010.