A Wireless Safety and Security Layer Architecture for Reliable Co-CPS
Ref: CISTER-TR-210604 Publication Date: 28 to 29, Jun, 2021
A Wireless Safety and Security Layer Architecture for Reliable Co-CPSRef: CISTER-TR-210604 Publication Date: 28 to 29, Jun, 2021
Modern multicore processors have the potential to provide raw computing power while being energy-efficient and cost-effective. While many of the systems have already deployed multicore processors for their operation, their adoption in time-sensitive applications is still active research. The main reason behind this is the architecture of a typical multicore processor. The typical architecture used in COTS platforms makes use of shared resources such as shared system bus, main memory, shared caches, etc., among all/several cores. A task can suffer inter-core interference from the co-running tasks while accessing these shared resources. This inter-core interference can impact the temporal behavior of the tasks and analyzing the worst-case timing behavior of a task becomes extremely challenging. The 3-phase task model was proposed to circumvent this problem by dividing the execution of each task into memory and execution phases. In the 3-phase task model, the memory accesses can only happen during a memory phase and a core can execute a memory phase while other cores are busy executing the execution phases. Even though some existing approaches focus on analyzing the schedulability of the 3-phase task model under partitioned scheduling, several open issues exist. In this paper, we identify the key open issues that are important to address in order to derive the schedulability analysis for the 3-phase task model using partitioned scheduling.
4th Doctoral Congress in Engineering (DCE 2021), Electrical and Computer Engineering.