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GI/ITG/GMA
Technical Committee “Dependability and Fault Tolerance” (VERFE) and
DFG Priority Program SPP 1500 “Dependable Embedded
Systems”
11th Workshop on Dependability and Fault
Tolerance (VERFE’15)
Focus
topic “Dependable Embedded Systems”
in
conjunction with ARCS 2015, Porto,
Portugal, March 24th – 27th, 2015
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Workshop Program
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09:00-09:30
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Omar Bousbiba
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ESSEN - An Efficient Single Round Signature
Protected Message Exchange Agreement Protocol for Wireless Distributed
Networks
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09:30-10:00
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Mischa Möstl,
Rolf Ernst
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Cross-Layer Dependency Analysis for
Safety-Critical Systems Design
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10:00-10:30
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Savas Takan, Berkin Guler, Tolga Ayav
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Model Checker-Based Delay Fault Testing
of Sequential Circuits
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10:30-11:00
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Break
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11:00-11:30
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Günther Nieß, Thomas Kern, Michael Gössel
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Error Detection Codes for Arbitrary
Errors Modeled by Error Graphs — Extended Abstract
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11:30-12:00
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Peter Sobe
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Reliability Impact of Data Deduplication
Techniques
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12:00-12:30
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Mohammad Shadi Alhakeem
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A Framework for Adaptive Software-Based
Reliability in COTS Many-Core Processors
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12:30-13:30
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Lunch
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13:30-14:00
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Martin Größl
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Dependable Systems Modeling and
Reliability Property Evaluation by Model Checking
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14:30-15:00
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Fevzi Belli
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Using Regular Expressions for
Self-Correction of Faults in Sequential Circuits
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Background and Focus
Although the basic
reliability of hardware and software components has improved over decades,
their increasing number causes severe problems. Moreover, in recent years it
can be observed that in an increasing number of devices, e.g. cars, digital
components are integrated into environments of other physical components. Here,
the complexity and number of interactions with these components creates
problems with regard to maintaining a dependable operation of the entire system
in case of faults or external disturbances.
While this is not a problem with
microprocessors there, shrinking feature sizes, higher complexity, lower
voltages, and higher clock frequencies increase the probability of design-,
manufacturing-, and operational faults, making fault tolerance techniques in
general purpose processors to be of crucial importance in the future. As simple
solutions (such as TMR) easily can get too expensive, the ability to trade
increased reliability against performance/power overhead will become important,
resulting in light-weight fault tolerance techniques implemented in hardware,
but controllable from higher software layers.
This workshop aims at
presenting contributions and work-in-progress from the research area of
dependable and fault tolerant computing in order to bring together scientists
working in related fields.
Topics
Contributions
on the topic of “Dependable Embedded Systems“ are of
particular interest; contributions on general topics of dependability and fault
tolerance are also welcome but not limited to:
·
reliability models for
hardware and software
·
modeling and simulation of
fault-tolerant systems
·
fault-tolerant systems and
system components
· formal verification of systems
· testing of hardware and software
· fault treatment
·
detection and correction of
transient faults
· quantitative assessment of reliability improvements
· safety-critical applications
· timeliness problems
· dependability of networks
· dependability of embedded systems
· highly available systems
· dependable organic computing
· self-organization within redundant systems
· dependable ubiquitous and pervasive computing
· composability of dependable systems
· dependable mechatronic systems / micro systems
·
dependability of mobile and
wireless systems
· robustness and robustness metrics
· validation and verification
·
fault models and fault model
abstraction
· fault-injection techniques
· software-controlled fault tolerance
·
on-chip backward recovery
techniques (e.g. pipeline flush and re-execution)
·
forward recovery techniques
(notification of higher layers)
· fault-tolerant caches
·
dynamic re-use of currently
unused resources in processors for fault-tolerance
Information for Authors
The
workshop will focus on research presentations as well as brainstorming
sessions.
The
proceedings of the Workshop will be published by the IEEE Computer Society,
through the IEEE Xplore Digital Library.
Two
kinds of contributions are welcome:
·
research papers documenting
results of scientific investigations and
·
position papers proposing strategies or discussing open problems.
Deadlines:
Submission:
EXTENDED December 19, 2014 (extended
abstracts (3-4 pages) or full papers, PDF)
to: bernhard.fechner@fernuni-hagen.de
Notification:
January 16, 2015
Camera-ready:
February
11, 2015 (max. 8 pages in IEEE format A4);
will appear in ARCS 2015 Workshop Proceedings.
Workshop:
March 24, 2015
VERFE'15
Workshop site: http://www.cister.isep.ipp.pt/arcs2015/verfe
Further
information about ARCS 2015: http://www.cister.isep.ipp.pt/arcs2015/
Workshop Chairs
B. Fechner, Univ. of Hagen, DE
K.-E. Großpietsch, St. Augustin, DE
Program Committee
L. Bauer, Karlsruhe Inst. of Technology, DE
F. Belli, Univ. of Paderborn, DE
R. Buchty, Karlsruhe Inst.
of Technology, DE
K. Echtle, Univ. of
Duisburg-Essen, DE
W.
Ehrenberger, Univ. of Fulda, DE
R.
Ernst, TU Braunschweig, DE
B.
Fechner, Univ. of Hagen, DE
M. Gössel, Univ. of Potsdam,
DE
E. Gramatova, Univ. of
Bratislava, SK
J.
Hülsemann, Siemens AG, Karlsruhe, DE
K.-E. Großpietsch, St.
Augustin, DE
J. Henkel, Karlsruhe Inst. of Technology, DE
J. Hursey, Oak Ridge
National Lab., US
J.
Kaiser, Univ. Magdeburg, DE
J.
Keller, Univ. Hagen, DE
H.-D.
Kochs, Univ. of Duisburg-Essen, DE
P.
Limbourg, Univ. of Duisburg-Essen, DE
M. Malek, Univ. of Lugano, IT
E. Maehle, Univ. of Lübeck, DE
M. Mock, Fraunhofer, St.
Augustin, DE
E. Nett, Univ. of Magdeburg,
DE
D. Nikolos, Univ. of Patras, DE
A. Pataricza, Univ. of
Budapest, HU
F.
Saglietti, Univ. of Erlangen-Nuremberg, DE
T. Sato, Univ. of Fukuoka, JP
M. Schulz, Lawrence Livermore National Lab., US
M. Shafique, Karlsruhe Inst.
of Technology, DE
P. Sobe, HTW Dresden, DE
J. Sosnowski, Univ. of
Warsaw, PL
A.
Stopp, Daimler AG, Berlin, DE
C.
Trinitis, TU Munich, DE
P.
Tröger, TU Chemnitz, DE
T.
Vierhaus, TU Cottbus, DE
M.
Walter, Siemens AG, Nuremberg, DE
H.
Wedde, TU Dortmund, DE
N.
Wehn, TU Kaiserslautern, DE
J. Weidendorfer, TU Munich,
DE
H.-Y. Youn, Univ. of Sungkyunkwan, KR
T. Yoneda, Univ. of Tokyo,
JP