Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers (Artifact)
Ref: CISTER-TR-181107 Publication Date: 2018
Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers (Artifact)
Ref: CISTER-TR-181107 Publication Date: 2018Abstract:
This artifact demonstrates the performance of the proposed worst-case memory stall analysis for a memory-regulated multicore with two memory controllers. The memory stall analysis is implemented in Java along with five different stall-cognisant bandwidth-to-core and task-to-core assignment heuristics. It evaluates the performance of these heuristics in terms of schedulability via experiments with synthetic task sets capturing different system characteristics. It also quantifies the cost in terms of extra stall for letting all cores benefit from the memory space offered by both controllers on the given multicore platform.
Muhammad Ali Awan
Pedro Souto
Konstantinos Bletsas
Benny Åkesson
Eduardo TovarDocument:
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DownloadPublished in Dagstuhl Artifacts Series (DARTS), Schloss Dagstuhl-Leibniz-Zentrum fuer Informatik, Volume 4, Issue 2, Article No 5, pp 5:1-5:3.
DOI:10.4230/DARTS.4.2.5.
ISSN: 2509-8195.
Record Date: 6, Nov, 2018
Short links for this page: www.cister.isep.pt/docs/10_4230_darts_4_2_5 www.cister.isep.pt/docs/cister_tr_181107 www.cister.isep.pt/docs/1439