Worst-Case Memory Traffic Analysis for Many-Cores using a Limited Migrative Model
Ref: CISTER-TR-130902 Publication Date: 19 to 21, Aug, 2013
Worst-Case Memory Traffic Analysis for Many-Cores using a Limited Migrative ModelRef: CISTER-TR-130902 Publication Date: 19 to 21, Aug, 2013
The ratio between the number of cores and memory subsystems (i.e. banks and controllers) in many-core platforms is constantly increasing, leading to non-negligible latencies of memory operations. Thus, in order to study the worst-case execution time of an application, it is no longer sufficient to only take into account its computational requirements, but also have to be considered latencies related to its memory operations.
In this paper we study a limited migrative model applied upon many-core platforms. This approach is based on a multi-kernel paradigm – a promising step towards scalable and predictable many-cores, which are essential prerequisites for the integration of such systems into the real-time embedded domain. Under that assumption, we present two analytical methods to obtain the worst-case memory traffic delays of individual applications. Through experiments we test the applicability of the proposed approaches to different scenarios, and draw practical conclusions concerning routing mechanisms and a distribution of memory operations across memory controllers.
19th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2013), IEEE, pp 42-51.