Memory Contention Analysis for 3-Phase Tasks
Ref: CISTER-TR-230503 Publication Date: 7 to 8, Jun, 2023
Memory Contention Analysis for 3-Phase TasksRef: CISTER-TR-230503 Publication Date: 7 to 8, Jun, 2023
In multiprocessor-based real-time systems, the main memory is identified as the main source of shared resource contention. Phased execution models such as the 3-phase task execution model has shown to be a good candidate to tackle the memory contention problem. It divides the execution of tasks into computation and memory phases that enable a fine-grained memory contention analysis. However, the existing work that focuses on the memory contention analysis for 3-phase tasks can overestimate the memory contention that can be suffered by the task under analysis due to the write requests. This overestimation can yield pessimistic bounds on the memory access times and memory contention suffered by tasks which in turn lead to pessimistic worst-case response time (WCRT) bounds. Considering the limitation of the state-of-the-art, this work proposes an improved memory contention analysis for the 3-phase task model. Specifically, we propose a memory contention analysis for the 3-phase task model by tightly bounding the memory contention suffered by the task under analysis due to the write requests. The proposed memory contention analysis integrates memory address mapping of tasks to improve the bounds on the maximum memory contention suffered by tasks.
Junior Researcher Workshop on Real-Time Computing, co-located with RTNS 2023 (JRWRTC 2023), Workshop session.