A Thermal-Aware Approach for DVFS-enabled Multi-core Architectures
Ref: CISTER-TR-221205 Publication Date: 2022
A Thermal-Aware Approach for DVFS-enabled Multi-core ArchitecturesRef: CISTER-TR-221205 Publication Date: 2022
Reducing thermal dissipation is vital for modern multi-core architectures to meet increasing computational demands. In this paper, we consider non-preemptive periodic tasks at two importance levels - Safety-Critical tasks (SC-tasks) and Best-Effort tasks (BE-tasks) - executing on a homogeneous multi-core processor with DVFS capabilities under thermal-aware design. We assume that tasks are scheduled according to a fully partitioned Fixed-Task-Priority (FTP) scheduler. Then, we propose two main contributions: (1) a new scheduling scheme, called NP-SafeSC, which reduces the responsiveness of SC-tasks as much as possible by procrastinating the execution of some BE-tasks; and (2) a new framework, called NP-ThermCare, that allows controlling both processor activity and the triggering of the cooling mechanism so that timing and thermal requirements are met. We provide a thorough analysis of our solutions, validate the results and evaluate their performance against a real-world use-case and intensive simulations. Our approach shows a consistent improvement of NP-SafeSC over NP-COIN in the responsiveness of all SC-tasks on each core. In particular, the improvement for the SC-task with the lowest priority reaches 39.53% for the real-world use-case and 45.17% for the simulations.
IEEE International Conference on Embedded Software and Systems (ICESS 2022).